1. Field of the Invention
The present invention relates to the field of manufacturing of semiconductor devices, and, more particularly, to the deposition of layers on a substrate.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements, such as transistors, capacitors, resistors and the like. These elements are connected internally to form complex circuits such as memory devices, logic devices and microprocessors. An improvement in the performance of integrated circuits requires a reduction of feature sizes. In addition to an increase in the speed of operation due to reduced signal propagation times, reduced feature sizes allow an increase in the number of functional elements in the circuit in order to extend its functionality.
FIG. 1 shows a schematic cross-sectional view of a field effect transistor 100 according to the state of the art. A substrate 101 comprises an active region 113. Shallow trench isolations 104, 105 isolate the active region 113 from neighboring circuit elements. An electrically conductive gate electrode 102 is formed over the substrate 101 and isolated from the substrate 101 by a gate insulation layer 112. The gate electrode 102 comprises a screening layer 103. A top surface of the gate electrode 102 is covered by a bottom antireflective coating (BARC) layer 120. The gate electrode 102 is flanked by sidewall spacers 110, 111. A raised source region 107 and a raised drain region 108 are formed on the substrate adjacent the sidewall spacers 110, 111.
Additionally, the field effect transistor 100 comprises an extended source region 114 and an extended drain region 115, which are formed in the substrate 101 below the raised source region 107 and the raised drain region 108, respectively. A portion of the extended source region 114, which is denoted as “source extension,” extends below the sidewall spacer 110 and is adjacent the gate electrode 102. Similarly, a portion of the extended drain region 115, denoted as “drain extension,” extends below the sidewall spacer 111 and is adjacent the gate electrode 102. Together, the raised source region 107 and the extended source region 114 form a source of the field effect transistor 100. Similarly, the raised drain region 108 and the extended drain region 115 together form a drain of the field effect transistor 100.
Due to the presence of the raised source region 107 and the raised drain region 108, the electric resistance of the field effect transistor 100 is reduced compared to a transistor without a raised source region and a raised drain region having a source region similar to the extended source region 114 and a drain region similar to the extended drain region 115.
Instead of providing the raised source region 107 and the raised drain region 108, one might alternatively reduce the resistivity of the field effect transistor 100 by providing a source region and a drain region in the substrate 101 adjacent the sidewall spacers 110, 111, and partially overlapping the extended source region 114 and the extended drain region 115. This, however, entails an enlarged area of the PN-junction between the source and drain, respectively, and the active region 113, which leads to greater signal delays due to an increase of the junction capacity. Therefore, providing the raised source region 107 and the raised drain region 108 clearly provides an advantage in high performance applications.
A method of forming a field effect transistor comprising a raised source region and a raised drain region will be described with reference to FIG. 1. First, the trench isolations 104, 105 and the active region 113 are formed in the substrate 101. Then, the gate insulation layer 112, the gate electrode 102 and the BARC layer 120 are formed over the substrate 101. These structures are formed using advanced techniques of ion implantation, deposition, oxidation and photolithography. Subsequently, the extended source region 114 and the extended drain region 115 are formed. This can be done by implanting ions of a dopant in the substrate 101. Parts of the substrate outside the transistor 100 that are not to be doped are covered by a layer of photoresist (not shown) that absorbs ions. Following implantation, the screening layer 103 and the sidewall spacers 110, 111 are formed adjacent the gate electrode 102 using deposition and anisotropic etching techniques. In particular, the sidewall spacers 110, 111 may be formed by means of known techniques comprising conformally depositing a layer of a sidewall spacer material and then performing an anisotropic etching process adapted to selectively remove the sidewall spacer material. Due to the anisotropy of the etching process, the sidewall spacers are left adjacent the gate electrode 102. Subsequently, a selective epitaxial growth process is performed to form the raised source region 107 and the raised drain region 108.
Selective epitaxial growth is a variant of chemical vapor deposition wherein process parameters such as temperature, pressure, and composition of the reactant gas are adapted such that a layer of material is deposited only in the exposed portions of the substrate 101, whereas there is no deposition on the trench isolations 104, 105, the BARC layer 120 and the sidewall spacers 110, 111. In particular, a layer of material is deposited in an area between the trench isolation 104 and the sidewall spacer 110 to form the raised source region 107. Additionally, a layer of material is deposited in an area between the sidewall spacer 111 and the trench isolation 105 to form the raised drain region 108. Additional layers 106, 109 may be formed in other regions where the substrate 101 is exposed.
In a particular example of a prior art process, the substrate comprises silicon. The screening layer 103, the BARC layer 120, the trench isolations 104, 105, and the sidewall spacers 110, 111 comprise a dielectric material, e.g., silicon dioxide and/or silicon nitride. In selective epitaxial growth, silane (SiCl4) and hydrogen (H2) are used as reactants. At growth temperature, these reactants react to silicon and hydrochloric acid. The reaction can proceed in both directions. The etching created in the back-reaction is important as it relates to inhibition of silicon growth on the areas covered by the dielectric.
After the formation of the source region 107 and the drain region 108, these regions are doped by means of implantation of ions of a dopant material.
Finally, an annealing may be performed to activate dopants in the active region 113, the extended source region 114, the extended drain region 115, the raised source region 107 and the raised drain region 108.
A problem of the prior art method of forming a field effect transistor comprising a raised source region and a raised drain region is that selective epitaxial growth is performed in ranges of process parameters where the deposited material grows epitaxially, adopting the crystal structure of the underlying substrate. Due to the crystalline structure, however, channeling effects may occur in the implantation of ions which may adversely affect the doping process.
Another problem of the prior art method of forming a field effect transistor comprising a raised source region and a raised drain region is that, in selective epitaxial growth, aggressive chemical compounds such as hydrochloric acid are generated. These compounds may damage the chemical vapor deposition apparatus and corrode components such as, e.g., vacuum pumps, unless elaborate countermeasures are performed.
Yet another problem of the prior art method of forming a field effect transistor comprising a raised source region and a raised drain region is that selective epitaxial growth is still not completely optimized and manufacturing proven.
In view of the above-mentioned problems, a need exists for techniques which allow the formation of a field effect transistor comprising a raised source region and a raised drain region and which are more compatible with existing processes used in the formation of integrated circuits.